In general, a computer bus is used to interface various devices or subsystems with other subsystems in a computer system. For example, a computer input/output bus may be used to interface input/output devices such as a modem, printer or graphics system to the CPU via an input/output bus controller. One problem that has confronted designers of such input/output buses in the past has been that, as technology develops, it is desirable to specify faster and faster bus clock frequencies for the bus in order to achieve maximum bandwidth during data transfers to and from the input/output devices coupled to it. On the other hand, not all input/output devices coupled to a particular bus may be capable of operating at the maximum specified bus clock frequency. Therefore, some bus architectures have been designed to accommodate input/output devices having a variety of maximum date transfer speeds. Two such bus architectures are disclosed in U.S. Pat. No. 5,491,814, titled "Apparatus Using a State Machine for Generating Selectable Clock Frequencies and a Fixed Frequency for Operating a Computer Bus," issued to Yee, et al. and assigned to Intel Corporation (hereinafter "Yee '814"). The two bus architectures disclosed in Yee '814 are reproduced herein at FIGS. 1 and 2.
Referring to FIG. 1, Yee '814 discloses using two separate buses 109 and 111 for slow and fast peripheral devices, respectively. Slow peripheral devices are coupled only to bus 109, and fast peripheral devices are coupled only to bus 111. Each of the two buses 109, 111 has its own bus controller 105, 107, and each bus controller 105, 107 has its own bus controller clock 106, 108. One of the bus controller clocks is fast (108), and one is slow (106). Both bus controllers 105, 107 are coupled to the processor or DMA controller 100. The system of FIG. 1 would be configured so that each of the two bus controllers decodes for a different range of addresses.
Referring now to FIG. 2, Yee '814 also teaches using a single bus 203 in lieu of the two buses 109, 111 shown in FIG. 1. In the system of FIG. 2, only one bus controller 200 is coupled to the single bus 203, but the single bus controller 200 is capable of operating at two different bus clock frequencies. The two different bus clock frequencies are produced by a dynamic bus clock generator 201 responsive to the output of a decode block 202. Both the bus controller 200 and the decode block 202 are coupled to processor or DMA controller 100. Fast and slow peripherals are associated with different address ranges, and decode block 202 monitors the target addresses for all bus cycles that are originated by processor or DMA controller 100. In turn, decode block 202 sends a decode output signal to bus clock generator 201. The result is that bus clock generator 201 clocks bus controller 200 either fast or slow depending on whether the target address for the bus cycle corresponds to a fast or slow peripheral. Yee '814 also teaches using signal screening logic 240 to either tri-state or force high or low certain of the signal lines comprising single bus 203 when the bus is operating at the faster of the two bus clock frequencies.
The bus architectures shown in FIGS. 1 and 2 are useful to the extent that they enable peripherals with different maximum speeds to be used together in a computer system more efficiently than in the past. However, several problems remain that the architectures of FIGS. 1 and 2 neither address nor solve:
First, it has been observed that when data transfers occur at fast bus clock frequencies such as 66 MHZ or greater, no more than two or three bus slots may be populated with peripherals. This is so because of the cumulative loading effect caused by parallel-connected peripherals.
Second, for multi-speed buses, the architecture of FIG. 2 has limited usefulness because the bus clock frequency is determined by the target address of each bus cycle. This scheme only works if processor or DMA controller 100 originates all of the bus cycles. (Decode block 202 is only able to decode signals generated by processor or DMA controller 100.) In modern systems, however, processor or DMA controller 100 would not be the only subsystem initiating bus cycles. Rather, it is now commonly the case that each of the peripherals occupying bus slots may from time to time initiate bus cycles. Even if the architecture of FIG. 2 were modified so that decode block 202 could see addresses generated by systems other than processor or DMA controller 100, the scheme of setting the bus speed based solely on the target address of the bus cycle would be inadequate to address the needs of such a modern system. For example, if a slow peripheral initiated a bus cycle to read data from a faster subsystem, the data transfer must occur at the slow speed of the originating peripheral. An architecture based on the teaching of Yee '814, however, would set the bus speed based on the target address and would therefore attempt to execute the bus cycle at the speed of the faster subsystem. The result would be a bus clock speed incompatible with the capabilities of the slower peripheral initiating the bus cycle.
A third problem involves the teaching by Yee '814 of the use of signal screening logic 240 during fast bus cycles. This mechanism would fail in modern systems for several reasons. First, all control signals must remain available to whichever peripheral is involved in a bus transaction. This cannot be achieved if a control signal on single bus 203 is simply tri-stated or forced high or low. Second, in modern systems wherein fast peripherals sample bus control signals at twice the rate of slow peripherals, it may happen that, during slow cycles, the fast peripherals may sample a control signal when the signal is indeterminate. Therefore, it becomes desirable to isolate fast peripherals from the control bus entirely during slow cycles, but to keep the slow peripherals coupled to the control bus during those cycles. This result is impossible to achieve with the signal screening logic 240 and single bus 203 taught by Yee '814. Moreover, Yee '814 only teaches the use of signal screening logic 240 during fast cycles, not slow ones.